A simple reconfigurable microprocessor in a 36 macrocell CPLD

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dc.contributor.authorWijesinghe, W.A.S.
dc.contributor.authorJayananda, M.K.
dc.contributor.authorSonnadara, D.U.J.
dc.date.accessioned2015-05-19T09:25:45Z
dc.date.available2015-05-19T09:25:45Z
dc.date.issued2011
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka, 39(3):p.261-266
dc.identifier.reportnumberFR 1608
dc.identifier.researchgrantnumberRG/2007/FR/003
dc.identifier.urihttps://dl.nsf.gov.lk/handle/1/19398
dc.publisherNSF:Colombo
dc.subjectInformation Communication Technology
dc.subjectData acquisition
dc.subjectComplex programmable logic device (CPLD)
dc.subjectField programmable gate arrays (EPGA)
dc.subjectMicrocontrollers
dc.subjectReconfigurable computing
dc.subjectHardware description language
dc.subjectVHDL
dc.titleA simple reconfigurable microprocessor in a 36 macrocell CPLD
dc.typeArticle

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