Integrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systems

Dewasurendra, S.D.Vidanapathirana, A.C.Abeyratne, S.G.2020-01-282020-01-282019-12Journal of the National Science Foundation of Sri Lanka,47(4):p.393-408https://dl.nsf.gov.lk/handle/1/25010Complex hybrid systemsCompositional testingCompositional verificationHardware-in-the-loop testingRuntime validationVandV – testing integrationIntegrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systemsArticle