Wijesinghe, W.A.S.Jayananda, M.K.Sonnadara, D.U.J.2010-07-062010-07-062008-9Journal of the National Science Foundation of Sri Lanka, 36(3):p.235-237https://dl.nsf.gov.lk/handle/1/5942Computer hardwareMultiplier hardware architectureField programmable gate array (FPGAs)Reconfigurable computingResource utilizationHardware description Language (VHDL)Computer ScienceInformation Communication TechnologyPerformance evaluation of multipliers in reconfigurable hardwareArticle