Design of fault-tolerant reversible Vedic multiplier in quantum cellular automata

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dc.contributor.authorKamaraj, A.
dc.contributor.authorMarichamy, P.
dc.date.accessioned2020-01-28T06:25:15Z
dc.date.available2020-01-28T06:25:15Z
dc.date.issued2019-12
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka,47(4):p.371-382
dc.identifier.urihttps://dl.nsf.gov.lk/handle/1/25003
dc.publisherNSF:Colombo
dc.subjectKMD gates
dc.subjectReversible logic
dc.subjectUrdhwa Triyakbhyam
dc.subjectVedic multiplication
dc.titleDesign of fault-tolerant reversible Vedic multiplier in quantum cellular automata
dc.typeArticle

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