Integrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systems

Dewasurendra, S.D.; Vidanapathirana, A.C.; Abeyratne, S.G.

Integrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systems

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JNSF_47_4_393.pdf (2.28 MB)

Date

2019-12

Authors

Dewasurendra, S.D.

Vidanapathirana, A.C.

Abeyratne, S.G.

Publisher

NSF:Colombo

Keywords

Complex hybrid systems, Compositional testing, Compositional verification, Hardware-in-the-loop testing, Runtime validation, VandV – testing integration

Citation

Journal of the National Science Foundation of Sri Lanka,47(4):p.393-408

URI

https://dl.nsf.gov.lk/handle/1/25010

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Journal of the National Science Foundation of Sri Lanka

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Integrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systems

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