Integrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systems

Simple item page
dc.contributor.authorDewasurendra, S.D.
dc.contributor.authorVidanapathirana, A.C.
dc.contributor.authorAbeyratne, S.G.
dc.date.accessioned2020-01-28T06:30:43Z
dc.date.available2020-01-28T06:30:43Z
dc.date.issued2019-12
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka,47(4):p.393-408
dc.identifier.urihttps://dl.nsf.gov.lk/handle/1/25010
dc.publisherNSF:Colombo
dc.subjectComplex hybrid systems
dc.subjectCompositional testing
dc.subjectCompositional verification
dc.subjectHardware-in-the-loop testing
dc.subjectRuntime validation
dc.subjectVandV – testing integration
dc.titleIntegrating runtime validation and hardware-in-the-loop (HiL) testing with V and V in complex hybrid systems
dc.typeArticle

Files

Original bundle

Now showing 1 - 1 of 1
Thumbnail Image
Name:
JNSF_47_4_393.pdf
Size:
2.28 MB
Format:
Adobe Portable Document Format
Download

License bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
0 B
Format:
Plain Text
Description:
Download

Collections

Journal of the National Science Foundation of Sri Lanka