Performance evaluation of multipliers in reconfigurable hardware

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dc.contributor.authorWijesinghe, W.A.S.en_US
dc.contributor.authorJayananda, M.K.en_US
dc.contributor.authorSonnadara, D.U.J.en_US
dc.date.accessioned2010-07-06T11:02:06Z
dc.date.available2010-07-06T11:02:06Z
dc.date.issued2008-9en_US
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka, 36(3):p.235-237en_US
dc.identifier.urihttps://dl.nsf.gov.lk/handle/1/5942
dc.publisherNational Science Foundation:Colomboen_US
dc.subjectComputer hardwareen_US
dc.subjectMultiplier hardware architectureen_US
dc.subjectField programmable gate array (FPGAs)en_US
dc.subjectReconfigurable computingen_US
dc.subjectResource utilizationen_US
dc.subjectHardware description Language (VHDL)en_US
dc.subjectComputer Scienceen_US
dc.subject.lccInformation Communication Technologyen_US
dc.titlePerformance evaluation of multipliers in reconfigurable hardwareen_US
dc.typeArticleen_US

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