A simple reconfigurable microprocessor in a 36 macrocell CPLD

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dc.contributor.authorWijesinghe, W.A.S.en_US
dc.contributor.authorJayananda, M.K.en_US
dc.contributor.authorSonnadara, D.U.J.en_US
dc.date.accessioned2012-06-27T06:22:27Z
dc.date.available2012-06-27T06:22:27Z
dc.date.issued2011en_US
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka39(3)pp.261-266en_US
dc.identifier.urihttps://dl.nsf.gov.lk/handle/1/9021
dc.publisherNSF. Colomboen_US
dc.subjectInformation Communication Technologyen_US
dc.subjectData acquisitionen_US
dc.subjectComplex programmable logic device (CPLD)en_US
dc.subjectField programmable gate arrays(EPGA)en_US
dc.subjectMicrocontrollersen_US
dc.subjectReconfigurable computingen_US
dc.subjectHardware description languageen_US
dc.subjectVHDLen_US
dc.titleA simple reconfigurable microprocessor in a 36 macrocell CPLDen_US
dc.typeArticleen_US

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