Implementation of data cache block (DCB) in shared processor using fi eld-programmable gate array (FPGA)

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dc.contributor.authorKarthick, R.
dc.contributor.authorMeenalochini, P.
dc.date.accessioned2021-04-07T06:08:19Z
dc.date.available2021-04-07T06:08:19Z
dc.date.issued2020-12
dc.identifier.citationJournal of the National Science Foundation of Sri Lanka,48(4):p.475-479
dc.identifier.urihttps://dl.nsf.gov.lk/handle/1/25244
dc.publisherNSF:Colombo
dc.subjectDynamic reconfiguration
dc.subjectMMPSoC
dc.subjectMultiprocessor
dc.titleImplementation of data cache block (DCB) in shared processor using fi eld-programmable gate array (FPGA)
dc.typeArticle

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